The use of an assembly of electrical conductors known as "bus" is common in electrical circuit designs. The bus transfers data and a bus clock signal synchronously; that is, the data transferred on the bus should be synchronized with the bus clock signal.
For highly reliable data transmission, a duplex bus system having two buses (one active bus through which data is currently being transferred and one stand-by bus for use when the active bus is in failure) is employed.
The bus clock signal of each bus of the duplex bus system is constantly monitored by a clock signal monitor and the data transfer will be switched to the stand-by bus when the active bus fails to transfer the bus clock signal properly. In other words, if the clock signal of the active bus does not supply pulses of a predetermined frequency, the data transfer will be made through the stand-by bus.
In a conventional clock failure detection scheme for a duplex bus, the failure of one clock signal is detected by using the other bus clock signal as a reference signal.
However, the conventional bus clock monitor cannot detect the failure of both bus clock signals occurring at the same time since there will be no reference signal working properly.